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lt3582/lt3582-5/lt3582-12 1 3582512fb typical application features applications description boost and single inductor inverting dc/dc converters with optional i 2 c programing and otp the lt ? 3582/lt3582-5/lt3582-12 are dual dc/dc converters featuring positive and negative outputs and integrated feedback resistors. the lt3582, with its built-in one time programming (otp), has con? gurable output settings via the i 2 c interface, including output voltage settings, power-up sequencing, power-down discharge, and output voltage ramp rates. lt3582 settings can be changed adaptively in the ? nal product, or set during manufacturing and made permanent using the built in non-volatile otp memory. the positive output voltage can be set between 3.2v and 12.775v in 25mv steps. the negative output voltage can be set between C1.2v and C13.95v in C50mv steps. the lt3582-5 and lt3582-12 are pre-con? gured at the factory for 5v and 12v outputs respectively, and as such, dont require the use of the i 2 c interface. the lt3582 series includes two monolithic converters, one boost and one inverting. the boost converter has an integrated power switch and output disconnect switch. the inverting converter uses a single inductor topology and includes an integrated power switch. both boost and inverting converters use a novel** control scheme resulting in low output voltage ripple while allowing for high conversion ef? ciency over a wide load current range. the lt3582 series is available in a 16-pin 3mm 3mm qfn. 12v supplies from a single 5v input n output voltages: 3.2v to 12.775v and C1.2v to C13.95v (lt3582) 5v and C5v (lt3582-5) 12v and C12v (lt3582-12) n digitally re-programmable (lt3582) via i 2 c for: output voltages power sequencing output voltage ramp rates n power-up defaults settable with non-volatile otp (lt3582) n i 2 c compatible interface (standard mode*) n all power switches integrated 350ma current limit (boost) 600ma current limit (inverting) n all feedback resistors integrated n input voltage range: 2.55v to 5.5v n low quiescent current 325a in active mode 0.01a in shutdown mode n integrated output disconnect n tiny 16-pin 3mm 3mm qfn package n amoled power n ccd power n general purpose dc/dc conversion l , lt, ltc, ltm, linear technology and the linear logo are registered trademarks of linear technology corporation. all other trademarks are the property of their respective owners. * input thresholds are reduced to allow communication with low voltage digital ics. (see electrical characteristics). ** patent pending ef? ciency and power loss lt3582 v in swp capp v neg C12v 85ma capp v pp sda scl ca gnd swn swn v outn v outp shdn input 4.5v to 5.5v v pos 12v 80ma 6.8h 10f 10nf 10nf rampn rampp 4.7f 4.7f 1f 6.8h 3582512 ta01a i 2 c interface optional on lt3582-5/lt3582-12 load current (ma) 0.1 35 efficiency (%) power loss (mw) 45 350 300 250 200 150 100 50 0 55 65 75 85 95 1 10 100 3582512 ta01b v outp v outn
lt3582/lt3582-5/lt3582-12 2 3582512fb pin configuration absolute maximum ratings v in voltage ..................................................................6v swp voltage .............................................................15v swn voltage ........................................................ ?16.5v capp voltage ............................................................15v capp-v outp voltage .................................... ?0.8v to 8v i capp-voutp ....................................................... 300ma v outp voltage ...........................................................15v v outn voltage ...................................................... ?16.5v rampp voltage ..........................................................3v rampn voltage ..........................................................3v shdn voltage ................................................ ?0.5 to 6v v pp voltage ...................................................?0.2 to 16v sda, ca, scl voltage .................................... ?0.5 to 6v operating junction temperature range (notes 3, 5) lt3582e ............................................ ?40c to 125c storage temperature range .............. ?65c to 150c (note 1) 16 15 14 13 5 6 7 8 top view 17 gnd ud package 16-pin (3mm 3mm) plastic qfn 9 10 11 12 4 3 2 1ca v outn swn swn swp capp capp v outp scl sda v pp gnd v in rampn rampp shdn t jmax = 125c, ja = 68c/w exposed pad (pin #17) is gnd, must be soldered to pcb symbol parameter conditions min typ max units v in_min minimum operating voltage l 2.4 2.475 2.55 v v in_max maximum operating voltage l 5.5 v i vin v in quiescent current ramp current con? gured to 1a, swoff bit active 325 450 a i vin_shdn v in quiescent current in shutdown v shdn = 0 0.01 0.5 a i capp_shdn capp quiescent current in shutdown v shdn = 0, v capp = 5.0v, v outp = 0v 0 0.5 a t off_minp minimum switch off time boost switch 100 ns t off_minn minimum switch off time inverting switch 125 ns order information lead free finish tape and reel part marking package description temperature range lt3582eud#pbf lt3582eud#trpbf lddb 16-pin (3mm 3mm) plastic qfn ?40c to 125c lt3582eud-5#pbf lt3582eud-5#trpbf ldvg 16-pin (3mm 3mm) plastic qfn ?40c to 125c lt3582eud-12#pbf lt3582eud-12#trpbf ldvh 16-pin (3mm 3mm) plastic qfn ?40c to 125c consult ltc marketing for parts speci? ed with wider operating temperature ranges. consult ltc marketing for information on non-standard lead based ? nish parts. for more information on lead free part marking, go to: http://www.linear.com/leadfree/ for more information on tape and reel speci? cations, go to: http://www.linear.com/tapeandreel/ electrical characteristics the l denotes the speci? cations which apply over the full operating temperature range, otherwise speci? cations are at t a = 25c. v in = 3.6v, v shdn n n s
lt3582/lt3582-5/lt3582-12 3 3582512fb electrical characteristics the l denotes the speci? cations which apply over the full operating temperature range, otherwise speci? cations are at t a = 25c. v in = 3.6v, v shdn = v in unless otherwise noted. (note 3) switching regulator characteristics symbol parameter conditions min typ max units t on_max maximum switch on-time inverting and boost switches 10 s i limit_p boost switch current limit l 285 350 430 ma i limit_n inverting switch current limit l 490 600 720 ma r on_p boost switch on-resistance i swp = 200ma 500 m r on_n inverting switch on-resistance i swn = C400ma 560 m i off_p boost switch leakage current into swp pin v swp = 5v 0.01 0.5 a i off_n inverting switch leakage current out of swn pin v in = 5.0, v swn = 0.0 0.01 1 a r on_dis output disconnect switch on-resistance v capp = 10v, rampp > 1.4v 1.4 i limit_dis output disconnect current limit l 124 155 186 ma i voutp_pds v outp power-down discharge current v outp = 8v 2.4 4.8 8.8 ma i capp_pds capp power-down discharge current capp = 8v 1.2 2.4 4.4 ma i voutn_pds v outn power-down discharge current v outn = C8v C1.4 C2.8 C4.2 ma t start-up con? guration start-up delay v in > v in_min and shdn > v shdn _vih to i 2 c enabled and power-up sequencing start l 64 128 s programmable output characteristics (note 6) symbol parameter conditions min typ max units v voutp positive output voltage lt3582-5 lt3582-12 l l 4.95 11.88 5 12 5.05 12.1 v v n_v outp positive v outp resolution (note 2) 9 bits v voutp_lsb v outp lsb (note 2) 25 mv v voutp_fs v outp full-scale voltage (note 2) code = bfh, v plus = 1 l 12.56 12.775 12.94 v v voutp_min v outp minimum voltage (note 2) code = 00h, v plus = 0 l 3.152 3.20 3.248 v v voutp_lr v outp line regulation code = bfh, 2.575 < v in < 5.5 C0.02 %/v v voutn negative output voltage lt3582-5 lt3582-12 l l C5.075 C12.1 C5 C12 C4.925 C11.868 v v n_v outn negative v outn resolution (note 2) 8 bits v voutn_lsb v outn lsb (note 2) C50 mv v voutn_fs v outn full-scale voltage (note 2) code = ffh l C14.2 C13.95 C13.7 v v voutn_min v outn minimum voltage (note 2) code = 00h l C1.23 C1.205 C1.18 v v voutn_lr v outn line regulation code = ffh, 2.575 < v in < 5.5 C0.01 %/v inl_v outp v outp integral nonlinearity (notes 2, 4) l 0.6 lsb dnl_v outp v outp differential nonlinearity (notes 2, 4) l 0.6 lsb inl_v outn v outn integral nonlinearity (note 2) l 0.85 lsb dnl_v outn v outn differential nonlinearity (note 2) l 0.85 lsb i ramp00 rampp/rampn pull-up current irmp code = 00 v rampp = 0.0v v rampn = 0.0v l 0.7 1.0 1.3 a i ramp01 rampp/rampn pull-up current (note 2) irmp code = 01 v rampp = 0.0v v rampn = 0.0v l 1.4 2.0 2.6 a
lt3582/lt3582-5/lt3582-12 4 3582512fb symbol parameter conditions min typ max units i ramp10 rampp/rampn pull-up current (note 2) irmp code = 10 v rampp = 0.0v v rampn = 0.0v l 2.8 4.0 5.2 a i ramp11 rampp/rampn pull-up current (note 2) irmp code = 11 v rampp = 0.0v v rampn = 0.0v l 5.6 8.0 10.4 a v vplus v outp voltage increase when v plus bit is set from 0 to 1 (note 2) 25 mv input/output pin characteristics symbol parameter conditions min typ max units v shdn _vih shdn input voltage high l 1.1 v v shdn _vil shdn input voltage low l 0.3 v v hyst_ shdn shdn input hysteresis 50 mv i shdn _bias shdn pin bias current v shdn = 1v 2.5 4.5 6.5 a v ca_vih ca input voltage high l 0.7 v in v v ca_vil ca input voltage low l 0.3 v in v v sda_vih sda input voltage high l 1.25 v v sda_vil sda input voltage low l 0.85 v v scl_vih scl input voltage high l 1.25 v v scl_vil scl input voltage low l 0.85 v v hyst input hysteresis sda, scl pins 80 mv i leak_ca ca input leakage current ca = 0v and 5.5v l 1 a i leak_scl scl input leakage current scl = 0v and 5.5v l 1 a i leak_sda sda input leakage current sda = 0v and 5.5v l 1 a c in input capacitance sda, scl pins 3 pf v sda_ol sda output low voltage 3ma into sda pin l 0.4 v v pp_range v pp voltage range for otp write (note 2) 13 15 v v ppuvlo undervoltage lockout for v pp pin (note 2) l 12.05 12.45 12.85 v i 2 c timing characteristics symbol parameter conditions min typ max units f scl serial clock frequency l 100 khz t low serial clock low period l 4.7 s t high serial clock high period l 4.0 s t buf bus free time between stop and start l 4.7 s t hd,sta start condition hold time l 4.0 s t su,sta start condition setup time l 4.7 s t su,sto stop condition setup time l 4.0 s t hd,datxmit data hold time transmitting lt3582 sending data to host l 300 ns t hd,datrcv data hold time receiving lt3582 receiving data from host l 0ns t su,dat data setup time l 250 ns t f sda fall time 400pf load, v in 2.5v l 250 ns electrical characteristics the l denotes the speci? cations which apply over the full operating temperature range, otherwise speci? cations are at t a = 25c. v in = 3.6v, v shdn = v in unless otherwise noted. (note 3) programmable output characteristics
lt3582/lt3582-5/lt3582-12 5 3582512fb electrical characteristics note 1: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. exposure to any absolute maximum rating condition for extended periods may affect device reliability and lifetime. note 2: lt3582 only. note 3: the lt3582e is guaranteed to meet performance speci? cations from 0c to 125c junction temperature. speci? cations over the C40c to 125c operating junction temperature range are assured by design, characterization and correlations with statistical process controls. note 4: these speci? cations apply to the v p trim bits in reg0 using a 50mv lsb and do not include the additional v plus trim bit. see registers and otp in the applications information section. note 5: this ic includes overtemperature protection that is intended to protect the device during momentary overload conditions. junction temperature will exceed the maximum operating junction temperature when overtemperature protection is active. continuous operation above the speci? ed maximum operating junction temperature may impair device reliability. note 6: output voltage is measured under non-switching test conditions approximating a moderate load current from the output.
lt3582/lt3582-5/lt3582-12 6 3582512fb typical performance characteristics switching frequencies (figure 13) load regulation (figure 13) output voltage (figure 13) quiescent current C not switching switch resistance switch current limit v outp and v outn pin current during normal operation output disconnect pmos current limit during normal operation output disconnect pmos on-resistance t a = 25c unless otherwise noted. load current (ma) 020406080 10 frequency (khz) 100 1000 10000 100 3582512 g01 v outp v outn load current (ma) 020406080 C1.00 C0.75 C0.50 C0.25 0 0.25 0.50 0.75 v out /v out (%) 1.00 100 3582512 g02 v outp v outn temperature (c) C50 C25 0 50 25 75 100 C0.45 C0.30 C0.15 0 0.15 0.30 0.45 v out /v out (%) 125 3582512 g03 v outp v outn v in (v) 2.5 3 3.5 4.5 4 5 5.5 250 270 290 310 330 350 370 390 quiescent current (a) 3582512 g04 input voltage (v) 2.5 3 3.5 4.5 4 5 5.5 0 0.1 0.2 0.3 0.4 0.5 0.6 o.7 switch resistance () 3582512 g05 v outn v outp temperature (c) C50 C25 0 50 25 75 125 100 200 300 400 500 600 700 switch current limit (ma) 3582512 g06 swn swp |v out | (v) 0 2.5 5 10 7.5 12.5 15 C20 C40 C60 C80 C100 0 20 40 60 80 pin current (a) 3582512 g07 current out of v outn pin current into v outp pin v p code set to 5v v p code set to 12v v n code set to C5v v n code set to C12v temperature (c) C50 C25 0 50 25 75 100 125 120 100 140 160 180 200 pmos current limit (ma) 3582512 g08 v capp (v) 24 8 61012 0.5 0 1 1.5 2 2.5 on-resistance () 3582512 g09
lt3582/lt3582-5/lt3582-12 7 3582512fb typical performance characteristics switching waveform at 1ma load (boost) switching waveform at 10ma load (boost) switching waveform at 100ma load (boost) switching waveform at 1ma load (inverting) switching waveform at 10ma load (inverting) load transient, v outn , 30ma to 60ma to 30ma steps load transient, v outp , 30ma to 60ma to 30ma steps power-up sequencing waveforms (puseq = 11) power-down discharge waveforms (puseq = 11, pddis = 1) 3582512 g10 v voutp 10mv/div ac coupled v swp 5v/div i l2 0.2a/div 5s/div 3582512 g11 v voutp 10mv/div ac coupled v swp 5v/div i l2 0.2a/div 2s/div 3582512 g12 v voutp 10mv/div ac coupled v swp 5v/div i l2 0.2a/div 200ns/div 3582512 g13 v voutn 20mv/div ac coupled v swn 10v/div i l1 0.2a/div 5s/div 3582512 g14 v voutn 50mv/div ac coupled v swn 10v/div i l1 0.2a/div 5s/div 3582512 g15 load current C20ma/div v voutn 0.1v/div ac coupled i l1 0.2a/div 50 s/div 3582512 g16 load current 20ma/div v outp 0.2v/div ac coupled i l2 0.2a/div 50s/div 3582512 g17 v rampn 1v/div v rampp 1v/div v voutp 5v/div v voutn 5v/div 5ms/div 3582512 g18 v rampp 1v/div v rampn 1v/div v voutn 5v/div v voutp 5v/div 5ms/div note: all waveforms on this page apply to figure 13.
lt3582/lt3582-5/lt3582-12 8 3582512fb pin functions ca (pin 1): i 2 c address select pin. tie this pin to v in to set the 7-bit address to 0110 001. tie to gnd for 1000 101. v outn (pin 2): negative output voltage pin. when the con- verter is operating, this pin is regulated to the programmed negative output voltage. place a ceramic capacitor from this pin to gnd. swn (pins 3, 4): negative switching node for the in- verting converter. this is the drain of the internal pmos power switch. connect one end of the inverting inductor to these pins. keep the trace area on these pins as small as possible. v in (pin 5): input supply pin and source of the pmos power switch. this pin must be bypassed locally with a ceramic capacitor. the operating voltage range of this pin is 2.55v to 5.5v. rampn (pin 6): soft-start ramp pin for the inverting converter. place a capacitor from this pin to gnd. a programmable current of 1a to 8a (lt3582) or 1a (lt3582-5/lt3582-12) charges this pin during start-up, limiting the ramp rate of v outn . this pin is discharged to gnd during shutdown. rampp (pin 7): soft-start ramp pin for the boost convert- er. place a capacitor from this pin to gnd. a programmable current of 1a to 8a (lt3582) or 1a (lt3582-5/lt3582-12) charges this pin during start-up, limiting the ramp rate of v outp . this pin is discharged to gnd in shutdown. shdn (pin 8): shutdown pin. drive this pin to 1.1v or higher to enable the part. drive to 0.3v or lower to shut down. includes an integrated 222k pull-down resistor. v outp (pin 9): output of the boost converter output disconnect circuit. a ceramic capacitor should be placed from this node to gnd. during shutdown, this pin is disconnected from the boost network which allows this pin to discharge to gnd, assuming a load is present to discharge the capacitance. capp (pins 10, 11): connect the boost output capacitor from these pins to gnd. during shutdown, the voltage on these pins will remain close to the input voltage due to the path through the boost inductor and schottky. during normal operation, capp will be boosted slightly higher than the programmed output voltage. swp (pin 12): positive switching node for the boost converter. this is the drain of the internal nmos power switch. connect one end of the boost inductor to this pin. keep the trace area on this pin as small as possible. gnd (pin 13): ground pin. tie to a local ground plane. proper pcb layout is required to achieve advertised per- formance; see the applications information section for more information. v pp (pin 14): programming voltage pin. drive this pin to 13-15v when programming the otp memory. float otherwise. a bypass capacitor should be placed from this node to gnd if v pp is used for programming. if v pp falls below 13v during otp programming, an internal fault bit, which can be read through the i 2 c interface, can be set high. sda (pin 15): i 2 c bidirectional data pin. tie to gnd or v in if unused. scl (pin 16): i 2 c clock pin. tie to gnd or v in if un- used. exposed pad (pin 17): ground pin. tie to a local ground plane. proper pcb layout is required to achieve advertised performance; see the applications information section for more information.
lt3582/lt3582-5/lt3582-12 9 3582512fb block diagram + C + C v in swn swn fbn vcn vcp otp rampn rampp v outn 3582512 bd capp gnd shdn chip enable 222k v pp scl sda ca otp swp capp v outp C + C + + C C + C + + 2v otp adjust otp adjust 0.80v 0.75v capp v outp v outn v in fbp fbn 50mv 2v output sequencing by otp i peak t off control i peak t off control q s qr q s q r variable delay variable delay C + + C + disconnect control serial interface, logic and otp output sequencing v in 0.80v fbp
lt3582/lt3582-5/lt3582-12 10 3582512fb operation the lt3582 series are dual dc/dc converters, each contain- ing both a boost and an inverting converter. operation can be best understood by referring to the block diagram. the boost and inverting converters each use a novel control technique, which simultaneously varies both peak inductor current and switch off time. this results in high ef? ciency over a large load range and low output voltage ripple. in addition, this technique further minimizes output ripple when the switching frequency is in the audio band. boost converter: the boost converter uses a grounded source nmos power transistor as the main switching ele- ment. the current in the nmos is constantly monitored and controlled, along with the off-time of the switch to achieve regulation of v outp . the v outp voltage is divided by the internal programmable (lt3582 only) resistor divider to create fbp . the voltage on fbp is compared to an internal reference and ampli? ed, creating an error signal on the vcp node which commands the appropriate peak inductor current and off time for the subsequent switching cycle. inverting converter: the inverting converter uses a power pmos transistor with the source connected to v in . this topology requires only one external inductor, instead of the normally required two inductors plus ? ying capacitor. regulation is achieved in a similar manner as the boost. output power-up sequencing: after an initial start-up delay (t start-up = 64s typical), the outputs v outp and v outn rise (in magnitude) simultaneously with the lt3582-5/ lt3582-12 or in one of four selectable sequences with the lt3582. using the i 2 c interface, the lt3582 outputs can be con? gured such that (1) they both rise simultane- ously, (2) v outp rises to regulation before v outn rises, (3) v outn rises to regulation before v outp rises, or (4) neither output rises. the outputs of the lt3582-5 and lt3582-12 are pre-con? gured to rise simultaneously. the ramp rates of the outputs are proportional to the ramp rates of their respective ramp pins. a capacitor is placed between each ramp pin and ground. the ramp pins are discharged during shutdown. once enabled, con? gurable (lt3582) or pre-con? gured (lt3582-5/lt3582-12) cur- rents charge each ramp pin in the desired sequence causing the outputs to rise. output power-down discharge: the power-down dis- charge feature is permanently enabled on the lt3582-5 and lt3582-12 and can be enabled or disabled through i 2 c on the lt3582. upon shdn falling, and when power- down discharge is enabled, internal transistors will acti- vate to assist in discharging the outputs toward ground. when power-down discharge is disabled, the chip powers down immediately after shdn falls and the outputs will discharge on their own depending on their external load capacitances and currents. otp memory (lt3582 only): the lt3582 includes 22 bits of user programmable output settings and 1 programming lockout bit. parameters such as positive and negative output voltages and power sequencing settings can be changed in real time with the integrated i 2 c interface. settings can then be made permanent by programming to the on-chip non-volatile otp (one time programmable) memory.
lt3582/lt3582-5/lt3582-12 11 3582512fb applications information figure 1. data transfer over i 2 c bus i 2 c interface the lt3582 series contains an i 2 c compatible interface allowing it to be digitally con? gured. the use of this interface is optional for the lt3582-5 and lt3582-12 as these parts are pre-con? gured at the factory. the ca, sda and scl pins can be grounded if the i 2 c interface is unused. the i 2 c interface has reduced input threshold voltages to allow for direct communication with low voltage digital ics (see electrical characteristics). i 2 c communication is disabled when shdn is low. after shdn rises, i 2 c communication is re-enabled after a delay of 64s (typical). the chip is a read-write slave device which allows the user to read the current settings and, for the lt3582, write new ones. most settings can be made permanent via the one-time-programmable memory. the chip will always enable using the data stored in otp and the lt3582 can be recon? gured after power-up. start and stop conditions when the bus is idle, both scl and sda are high. a bus master signals the beginning of a transmission with a start condition by transitioning sda from high to low while scl is high, as shown in figure 1. when the master has ? nished communicating with the slave, it issues a stop condition by transitioning sda from low to high while scl is high. the bus is then free for another transmission. acknowledge the acknowledge signal (ack) is used in handshaking between transmitter and receiver to indicate that the most recent byte of data was received. the transmitter always releases the sda line during the acknowledge clock pulse. when the slave is the receiver, it pulls down the sda line so that it remains low during this pulse to acknowledge receipt of the data. if the slave fails to acknowledge by leaving sda high, then the master may abort the transmission by generating a stop condition. when the master is receiving data from the slave, the master pulls down the sda line during the clock pulse to indicate receipt of the data. after the last byte has been received the master leaves the sda line high (not acknowledge) and issues a stop condition to terminate the transmission. device addressing the lt3582 series supports two 7-bit chip addresses depending on the logic state of the ca pin. the addresses are 0110 001 (ca = 1) and 1000 101 (ca = 0). also, there are seven internal data byte locations as shown in table 1. otp0-otp2 are the otp memory bytes. reg0-reg2 are the corresponding volatile registers used for storing alternate settings. finally, the command register (cmdr) is used for additional control of the chip. 3582512 f01 scl sda r/ w chip address start condition stop condition ack data ack data 1-7 b7 - b0 b7 - b0 a6 - a0 89 1-7 8 9 1-7 8 s p 9 ack
lt3582/lt3582-5/lt3582-12 12 3582512fb all data bytes can be read from their assigned register addresses. since they share the same register addresses, reads of the otp and reg data bytes are differentiated by their corresponding rsel (register select) bits in the cmdr register. all data written to register addresses 0-2 is stored in rego-reg2. regardless of the rsel bits, otp bytes cannot be written directly. see the otp programming section for more information. data transfer protocol the lt3582 series supports 8-bit data transfers in the transaction formats shown in figures 2 and 3. multiple data bytes can only be transferred by issuing multiple transactions. figure 2 shows the required format for writing a byte of data to the lt3582 series. again, the chip address depends on the ca pin logic state. s chip addr w a reg addr a data a p 0110 001 or 1000 101 0 0 00000b2:b0 0 b7:b0 0 from master to slave a: acknowledge (low) from slave to master a : not acknowledge (high) r: read bit (high) w write bit (low) s: start condition p: stop condition figure 2. i 2 c byte write transaction a byte of data is read from the lt3582 series using the format shown in figure 3. this transaction requires four i 2 c bytes to read one byte of chip data and must be repeated for each subsequent byte of data that is read. s chip addr w a reg addr a 0110 001 or 1000 101 0 0 00000b2:b0 0 lt3582 chip con? guration settings such as output voltages and sequencing are digitally programmable. the chip uses settings from either the reg or otp bytes, depending on the states of the corresponding rsel bits (0 for otp and 1 for reg). during shutdown the rsel bits are reset low. as a result, the initial con? guration comes from the otp data bytes. after power-up, the con? guration can be changed by writing new settings to the appropriate reg data byte(s) then setting the corresponding rsel bit(s). finally, data in the reg bytes can be permanently programmed to otp by applying voltage to the v pp pin and setting the wotp bit in the command register. see the otp programming section for more information. lt3582-5/lt3582-12 chip con? guration the lt3582-5/lt3582-12 are shipped from the factory with the otp memory pre-programmed and locked which prohibits subsequent changes to the con? guration. the con? guration can still be read through the i 2 c bus and the rst and swoff bits of the cmdr register (described later) are functional. the following sections describe the various con? gurable features of the lt3582. the lt3582-5 and lt3582-12 are pre-con? gured as follows: v p and v n are programmed for 5v or 12v respectively, lock = 1, irmp = 00, pddis = 1, puseq = 11 and v plus may be 1 or 0. since lock = 1, subsequent con? guration changes are prohibited. see con? guration lockout (lock bit) for more information. registers and otp the registers and otp bytes for the lt3582 series are organized as shown in table 1. the cmdr is reset to 00h upon power-up, during shutdown and during undervoltage and thermal lockouts. reg0-reg2 are never reset and must always be loaded with valid data before use. the lt3582s otp memory is shipped with all 0s, and as a result, the puseq bits are con? gured to disable the outputs. the puseq bits must be recon? gured to enable the outputs. applications information s chip addr r a data a p 0110 001 or 1000 101 1 0 b7:b0 1 figure 3. i 2 c byte read transaction
lt3582/lt3582-5/lt3582-12 13 3582512fb cmdr: the command register is used to control various functions of the chip. during shutdown and power-up the cmdr is initialized to 00h. the rsel (register select) bits are functional only for the lt3582. the lt3582-5 and lt3582-12 function as if the rsel bits are always 0. these bits perform three functions: ? each rsel bit instructs the chip whether to use the con? guration data from the corresponding otp byte (rselx = 0) or the reg byte (rselx = 1). changing an rselx bit immediately updates the chip con? guration. ? each rsel bit determines if i 2 c reads return data from the corresponding otp byte (rselx = 0) or the reg byte (rselx = 1). ? otp programming only programs data to the bytes with corresponding rsel bits set high. setting the swoff bit immediately disables the boost and inverting power switches and opens the output dis- connect pmos switch. it is recommended to set this bit before writing new con? guration data. this can prevent unexpected chip behavior while modifying the con? gura- tion and also forces a soft-start after swoff is cleared (see soft-start and power-up sequencing ). writing 1 to the rst bit resets the internal i 2 c logic and the cmdr register. reading bit 6 of the cmdr returns the fault bit indicating if an otp programming attempt may have failed. fault is cleared during reset, power-up, or by writing a 1 to the cf (clear fault) bit. conditions that set the fault bit are (1) otp programming in which the v pp voltage is too low or (2) attempted otp programming when the lock bit is set. otp write attempts that set the fault bit due to low v pp voltage should be considered failures and the device should be discarded. attempts to re-program the otp memory after the fault bit has been set are not recommended. finally, setting the wotp bit starts the otp programming. table 1: lt3582 series register map register address regis- ter name bit bit name description 00h reg0/ otp0 7:0 v p v outp output voltage (00h=3.2v, bfh = 12.75v) 01h reg1/ otp1 7:0 v n v outn output voltage (00h=1.2v, ffh = 13.95v) 7 - reserved, write to 0 6 lock lockout bit: see the otp programming lockout section. 02h reg2/ otp2 5v plus v outp output voltage bit: increase v outp by ~25mv 4:3 irmp rampp and rampn pull-up current: i ramp = (2) irmp a 2 pddis power-down discharge enable. puseq must be 11 if set. 1:0 puseq power-up sequencing: 00 = outputs disabled, 01 = v outn ramp 1st, 10 = v outp ramp 1st, 11 = both ramp together 7 wotp write otp memory 6 cf/ fault clear fault/otp programming fault 5 rst reset 4 swoff switches-off 04h cmdr 3 - reserved, write to 0 2 rsel2 register select 2 (0 = otp2, 1 = reg2) 1 rsel1 register select 1 (0 = otp1, 1 = reg1) 0 rsel0 register select 0 (0 = otp0, 1 = reg0) otp0/reg0 and otp1/reg1: data in addresses 00h and 01h is used to set the output voltages of the boost and inverting converters respectively. see setting the output voltages for more information. applications information
lt3582/lt3582-5/lt3582-12 14 3582512fb otp2/reg2: data in address 02h con? gures the output voltage sequencing, sets a ? ne voltage adjust for v outp , and determines if further otp programming is permitted or not. proper uses of the bits in address 02h are discussed in the following sections. setting the output voltages (v p , v plus and v n bits) the lt3582 series contains two resistor dividers which are programmable in the lt3582, to set the output voltages. the positive output voltage v outp is adjustable in 25mv steps by setting the v p bits in reg0/otp0 in addition to the v plus bit in reg2/otp2. v outp = 3.2v + (v p ? 50mv) + (v plus ? 25mv) where: v p = an integer value from 0 to 191 v plus = 0 or 1 the v outn voltage is adjustable in C50mv steps by setting the v n bits in reg1/otp1. v outn = C1.2v C (v n ? 50mv) where: v n = an integer value from 0 to 255 dynamically changing the output voltage (lt3582 only): after output regulation has been reached, its possible to change the output voltages by writing new values to the v n or v p bits. when reducing the magnitude of an out- put voltage, it will decay at a rate dependent on the load current and capacitance. con? guring a large increase in magnitude of an output voltage can cause a large increase in switch current to charge the output capacitor. before recon? guring the outputs, consider forcing a soft-start by asserting the swoff bit before writing the new v p or v n codes. subsequently clearing swoff initiates the new soft-start sequence. soft-start/output voltage ramping (irmp bits) the lt3582 series contains soft-start circuitry to control the output voltage ramp rates, therefore limiting peak switch currents during start-up. high switch currents are inherent in switching regulators during start-up since the feedback loop is saturated due to v out being far from its ? nal value. the regulator tries to charge the output capacitor as quickly as possible which results in large currents. capacitors must be connected from rampp and rampn to ground for soft-start. during shutdown or when the swoff bit is set, the ramp capacitors are discharged to ground. after shdn rises or swoff is cleared, the capacitors are charged by programmable (lt3582 only) currents, thus creating linear voltage ramps. the v out voltages ramp in proportion to their respective ramp voltages according to: v out _ ramp _ rate = v out 0.8v ? ? ? ? ? ? ? i ramp c ramp ? ? ? ? ? ? volts / sec proportionality constant ramp pin ramp rate (v/sec) where: i ramp = ramp pin charging current set by irmp bits (1a, 2a, 4a or 8a for lt3582, 1a for lt3582-5/lt3582-12) c ramp = external ramp pin capacitor (farads) v out = output voltage during regulation for example, selecting i ramp = 1a, c ramp = 10nf and v outp = 12v results in a power-up ramp rate of 1.5volt/ms (see figure 6). ramp rates less than 1-10v/ms generally result in good start-up characteristics. the outputs should linearly follow the rampx voltages with no distortions. figure 7 shows an excessive start-up ramp rate of ~120v/ms in which applications information
lt3582/lt3582-5/lt3582-12 15 3582512fb several start-up issues have occurred: a) the expected v outp ramp up path is not followed b) inductor current ringing occurs c) the v outp ramp rate is limited due to the output disconnect current limit being reached d) ad- ditional ringing occurs when the capp pin starts charging e) output voltage overshoot occurs because the inductor currents are maximized during the output ramp-up. in some cases it may be desirable to use only one ramp pin capacitor. in cases where puseq = 11 (see the power- up sequencing section) the rampp and rampn pins can be connected together and to a single capacitor. in this case the capacitor will charge with twice the current con? gured by the irmp bits. ramping v outp from ground: the lt3582 series has the unique ability to generate a smooth v outp voltage ramp starting from ground and continuing all the way up to regulation (see figure 6). this ability is not possible with typical boost converters in which the output is taken from the cathode of the schottky diode (capp node in figure 5). l1 d1 swp c1 v outp c3 v in c2 capp lt3582 series disconnect control load 3582512 f05 applications information the lt3582 series incorporates an output disconnect pmos allowing v outp to be grounded during shutdown. once enabled, the disconnect control circuit actively drives the pmos gate allowing v outp to ramp up linearly as shown in figure 6. once v outp reaches regulation, the pmos is fully turned on to reduce resistance and improve ef? ciency. power-up sequencing (puseq bits) once enabled, the part requires a delay of t start-up (64s typ) to properly con? gure itself. once con? gured, the order in which v outp and v outn ramp to regulation is controlled by the puseq bits. the combinations available for the lt3582 are shown in table 2. the lt3582-5/lt3582-12 are pre-con? gured with the 11 combination. table 2. power-up sequences puseq[1:0] power-up sequence 00 outputs are disabled, neither output ramps up 01 v outn ramps up 1st, followed by v outp 10 v outp ramps up 1st, followed by v outn 11 both v outp and v outn ramp-up starting at the same time. selecting the 01 or 10 combinations cause one of the out- puts to start ramping shortly after shdn rises. the ramp rate of v out is controlled by the ramp pin as discussed in the soft-start section. after v out nears its target regula- figure 5. boost converter topology figure 6. v outp soft-start ramping from ground figure 7. v outp soft-start with excessive ramp rate 3582512 f06 capp 2v/div i l2 0.2a/div v rampp 0.2v/div v outp 2v/div 1ms/div 3582512 f07 v outp 3v/div v rampp 0.5v/div capp 3v/div i l2 0.2a/div 50s/div a c e bd
lt3582/lt3582-5/lt3582-12 16 3582512fb tion voltage, the remaining output is activated and ramps under control of its respective ramp pin (see figure 8). the power-up sequencing concludes when both outputs have reached regulation. evaluating puseq settings (lt3582 only): after shdn rises, the lt3582 uses the puseq con? guration found in otp . the effects of differing puseq settings can be observed without writing to otp by taking the following actions: 1. write the swoff bit high, stopping both converters and discharging the ramp pins. 2. write the desired settings to the puseq bits in reg2. 3. set the rsel2 bit high which selects the reg2 con- ? guration settings. 4. write swoff low which restarts both converters. this will initiate the desired power-up sequence that can be observed with an oscilloscope. power-down discharge (pddis bit) the pddis bit is used to enable power-down discharge. this bit is pre-con? gured to a 1 for the lt3582-5 and lt3582-12, thus enabling power-down discharge.setting pddis = 0 disables the power-down discharge causing the chip to shut down immediately after shdn falls. applications information the pddis bit must only be set in conjunction with puseq being set to 11. driving shdn low, with power- down discharge enabled (pddis = 1) causes the chip to power-down after ? rst discharging the output voltages. speci? cally, driving shdn low causes the following se- quence of events to happen: 1. both converters are turned off. 2. discharge currents are enabled to discharge the output capacitors ? see electrical characteristics for i voutp-pds and i capp-pds which help discharge v outp and capp ? see electrical characteristics for i voutn-pds which helps discharge v outn 3. the chip waits until the output voltages have discharged to within ~0.5v to ~1.5v of ground. 4. discharge currents are disabled and the lt3582 powers down. since the lt3582 series wont power-down until both outputs are discharged (when power-down sequencing is enabled), make sure v outp and v outn can be grounded. this is not a problem in most topologies. however, read the section output disconnect operating limits for ad- ditional information. figure 8. power-up sequencing (puseq = 10) 3582512 f08 v voutp 5v/div v voutn 5v/div v rampp 0.5v/div v rampn 0.5v/div 5ms/div rampn rampp
lt3582/lt3582-5/lt3582-12 17 3582512fb con? guration lockout (lock bit) after a desired con? guration is programmed into otp , the lock bit can be set to prohibit subsequent changes to the con? guration. the lt3582-5 and lt3582-12 are precon- ? gured with the lock bit set to a logic 1 which: ? forces the chip to use the otp con? guration only. ? forces all i 2 c reads from addresses 0-2 to return otp data. ? prohibits any further programming of the otp memory. any further attempts to program otp leaves the otp memory unchanged and sets the fault bit in the cmdr. the lock otp bit is set by programming a logic 1 into bit 6 of otp2. regardless of the rsel2 setting, i 2 c reads of the lock bit always indicate the locked or unlocked state of the otp memory. otp programming (lt3582 only) the lt3582 contains one time programmable non-vola- tile memory to permanently store the chip con? guration. before programming, its recommended to set the swoff bit to disable switching activity and prevent unexpected chip behavior while the con? guration is being changed. programming involves the transfer of information from the reg bytes to the otp bytes. therefore, valid data must ? rst be written to the desired reg bytes. after the reg bytes are written, they are selected by setting the cor- responding rsel bits in the cmdr. this forces the chip into the desired con? guration and selects those bytes for programming to otp . after 15v has been applied to v pp , the wotp bit is set in the cmdr to start the programming. finally, the wotp bit is cleared to ? nish the programming. an example programming algorithm is given below. otp programming draws about 3ma to 6ma per bit from the v pp pin. it is possible to program all 23 bits simultane- ously (up to ~138ma), but it is recommended that one byte is programmed at a time to reduce noise on v pp caused by the sudden change in current. a 1-10f v pp bypass capacitor is also recommended to prevent voltage droop after programming begins. also, avoid hot-plugging v pp which results in very fast voltage ramp rates and can lead to excessive voltage on the v pp pin. example otp programming algorithm: 1. apply 15v to the v p-p pin. this can be done at any time before step 5. 2. write 50h to the cmdr. this disables the power switches during programming by setting the swoff bit in the cmdr. this also clears the fault bit. 3. write desired data to reg0-reg2. 4. write 11h to the cmdr. this selects reg0 for pro- gramming while keeping the switches off. 5. write 91h to the cmdr. this programs the reg0 data to otp0. 6. write 11h to the cmdr. this command can be sent im- mediately after step 5. this stops the programming. 7. read the cmdr and verify that the fault bit is not set. 8. repeat steps 4-7 for the remaining bytes that need programming. 9. write 10h to the cmdr. this selects the otp data for read veri? cation. 10. read the otp data and verify the contents. 11. write 00h to cmdr. this enables the power switches and the chip will operate from the otp con? gura- tion. 12. float the v pp pin. this can be done at any time after step 8. applications information
lt3582/lt3582-5/lt3582-12 18 3582512fb choosing inductors several series of inductors that work well with the lt3582 series are listed in table 3. this table is not complete, and there are many other manufacturers and parts that can be used. consult each manufacturer for more detailed information and for their entire selection of related parts, as many different sizes and shapes are available. table 3. inductor manufacturers coilcraft lps3008-lps4018 series, xpl2010 series www.coilcraft.com murata lqh32c, lqh43c series www.murata.com sumida cdrh26d09, cdrh26d11, cdrh3d14 series www.sumida.com tdk vlf and vlcf series www.tdk.com wrth elektronik we-tpc series type t, th, xs and s www.we-online.com inductances of 2.2h to 10h typically result in a good tradeoff between inductor size and system performance. more inductance typically yields an increase in ef? ciency at the expense of increased output ripple. less inductance may be used in a given application depending on required ef? ciency and output current. for higher ef? ciency, choose inductors with high frequency core material, such as ferrite, to reduce core losses. also to improve ef? ciency, choose inductors with more volume for a given inductance. the inductor should have low dcr (copper-wire resistance) to reduce i 2 r losses, and must be able to handle the peak inductor current without saturating. to minimize radiated noise, use a toroidal or shielded inductor (note that the inductance of shielded types will drop more as current increases, and will saturate more easily). peak current rating: real inductors can experience a drop in inductance as current and temperature increase. the inductors should have saturation current ratings higher than the peak inductor currents. the peak inductor cur- rents can be calculated as: i pk ? i limit + v lswon ? t os l ma where: i pk = peak inductor current i limit = typically 350ma for boost and 600ma for inverting l = inductance in h v lswon = maximum inductor voltage when the power switch is on. typically max v in for the boost and inverting converters. t os = 100 for boost and 125 for inverting applications information
lt3582/lt3582-5/lt3582-12 19 3582512fb maximum load currents: use one of the following equa- tions to estimate the maximum output load current for the positive and negative output voltages: i outp = v in(min) v outp ? ? ? ? ? ? ? i pk ? t off _ min ?(v outp + 0.5 ? v in(min) ) 2?l ? ? ? ? ? ? ? 0.8 or i outn = v in(min) v in(min) + |v outn | ? ? ? ? ? ? ? ? ? i pk ? t off _ min ?(|v outn | + 0.5) 2?l ? ? ? ? ? ? ? 0.8 where: v out = regulation voltage v in(min) = minimum input voltage. i pk = peak inductor current. see the peak current rating section. use minimum i limit rating for these calculations. = power conversion ef? ciency (about 88% for boost or 78% for inverting) t off_min = minimum switch off time. typically 100ns for boost and 125ns for inverting. i out = output load current for example, if v outp = 10v, v outn = C10v, v in = 5v, and l = 4.7h then i outp = 117ma and i outn = 105ma. note: the 155ma (typ) current limit of the output dis- connect pmos (see electrical characteristics) may limit maximum i outp unless capp is shorted to v outp . see the improving boost converter ef? ciency section. maximum slew rate: lower inductance causes higher current slew rates which can lead to current limit over- shoot. choose an inductance higher than l min to limit the overshoot: l min = v in(max) ? 0.2h where v in(max) is the maximum input voltage. using the previous example v in = 3v, l min = 0.6h. capacitor selection the small size and low esr of ceramic capacitors makes them suitable for most lt3582 series applications. x5r and x7r types are recommended because they retain their capacitance over wider voltage and temperature ranges than other types such as y5v or z5u. a 4.7f input capaci- tor and a 2.2f to 10f output capacitor are suf? cient for most lt3582 series applications. always use a capacitor with a suf? cient voltage rating. many capacitors rated at 2.2f to 10f, particularly 0805 or 0603 case sizes, have greatly reduced capacitance at the desired output voltage. generally a 1206 capacitor will be adequate. a 0.22f to 1f capacitor placed on the capp node is recommended to ? lter the inductor current while the larger 2.2f to 10f placed on the v outp and v outn nodes will give excellent transient response and stability. avoid placing large value capacitors (generally > 6.8f) on both capp and v outp . this con? guration can be less stable since it creates two poles, one at the capp pin and the other at the v outp pin, which can be near each other in frequency. table 4 shows a list of several capacitor manufacturers. consult the manufacturers for more detailed information and for their entire selection of related parts. table 4. ceramic capacitor manufacturers manufacturer phone url kemet 408-986-0424 www.kemet.com murata 814-237-1431 www.murata.com taiyo yuden 408-573-4150 www.t-yuden.com tdk 847-803-6100 www.tdk.com diode selection schottky diodes, with their low forward voltage drops and fast switching speeds, are recommended for use with the lt3582 series. the diodes inc. b0540ws is a very good choice in a small sod-323 package. this diode is rated to handle an average forward current of 500ma and performs well across a wide temperature range. schottky diodes with very low forward voltage drops are also available. these diodes may improve ef? ciency at moderate and cold temperatures, but will likely reduce ef? ciency at higher temperatures due to excessive reverse leakage currents. applications information
lt3582/lt3582-5/lt3582-12 20 3582512fb output disconnect operating limits the lt3582 series has a pmos output disconnect switch connected between capp and v outp . during normal operation, the switch is closed and current is internally limited to about 155ma (see figure 9). make sure that the output load current doesnt exceed the pmos current limit. exceeding the current limit causes a signi? cant rise in pmos power consumption which may damage the device. during shutdown, the pmos switch is open and capp is isolated from v outp up to a voltage difference of 5-5.5v. in most cases this allows v outp to discharge to ground. however, when the boost inductor input exceeds 5.5v, the capp-v outp voltage may exceed 5v allowing some current ? ow through the pmos switch. in addition, applying capp- v outp voltages in excess of 5.7v(typical) may activate internal protection circuitry which turns the pmos on (see figure 10). if the current is not limited, this can lead to a sharp increase in the pmos power consumption and may damage the device. if this situation cannot be avoided, limit pmos power consumption to less than 1/3 watt (about 50ma at 7v) to avoid damaging the device. refer to the absolute maximum ratings table for maximum limits on capp-v outp voltages and currents. improving boost converter ef? ciency the ef? ciency of the boost converter can be improved by shorting the capp pin to the v outp pin (see figure 11). the power loss in the pmos disconnect circuit is then made negligible. in most applications, the associated capp pin capacitor can be removed and the larger v outp capacitor can adequately ? lter the output voltage. applications information lt3582 v in capp capp v outp sda v pp ca shdn gnd swn swn v outn 3582512 f12 scl swp 81 16 15 14 9 10 11 5 12 76 2 13 3 4 rampn rampp c1 i load figure 10. pmos current vs voltage during shutdown figure 11. improved ef? ciency i capp-voutp 20a/div v capp-voutp 1v/div 3582512 f11 figure 9. pmos current vs voltage during normal operation capp-v outp (mv) 0 100 200 400 300 500 0 20 40 100 80 120 140 60 160 180 pmos current (ma) 3582512 f10
lt3582/lt3582-5/lt3582-12 21 3582512fb applications information note that the ripple voltage on v outp will typically increase in this con? guration since the output disconnect pmos, when not shorted, helps to create an rc ? lter at the output. also, if the v outp pin is shorted to capp , the power-down discharge should not be enabled. v outp cannot be discharged to ground during shutdown due to the path from v in to v outp through the external inductor and diode. finally, due to the path from v in to v outp , current will ? ow through the integrated feedback resistor whenever voltage is present on v in . inrush current when the boost inductor input voltage (usually v in ) is stepped from ground to the operating voltage, a high level of inrush current may ? ow through the inductor and schottky diode into the capp capacitor. conditions that increase inrush current include a larger more abrupt voltage step at the inductor input, larger capp capacitors and inductors with low inductances and/or low saturation currents. for circuits that use output capacitor values within the recommended range and have input voltages of less than 5v, inrush current remains low, posing no hazard to the devices. in cases where there are large input voltage steps (more than 5v) and/or a large capp capacitor is used, inrush current should be measured to ensure safe operation. thermal lockout if the die temperature reaches approximately 147c, the part will go into thermal lockout. in this event, the chip is reset which turns off the power switches and starts to discharge the ramp capacitors. the part will be re-enabled when the die temperature drops by about 3.5c. board layout considerations as with all switching regulators, careful attention must be paid to the pcb board layout and component placement. to maximize ef? ciency, switch rise and fall times are made as short as possible. to prevent electromagnetic interference (emi) problems, proper layout of the high frequency switching path is essential. the voltage signals of the swp and swn pins have sharp rising and falling edges. minimize the length and area of all traces connected to the swp/swn pins and always use a ground plane under the switching regulator to minimize interplane coupling. suggested component placement is shown in figure 12. make sure to include the ground plane cuts as shown in figure 12. the switching action of the regulators can cause large current steps in the ground plane. the cuts reduce noise by recombining the current steps into a continuous ? ow under the chip, thus reducing di/dt related ground noise in the ground plane. figure 12. suggested component placement (not to scale) ground plane vias to ground plane under pin 17 required to improve thermal performance 3582512 f13 v outp c outp c capp c outn v outn gnd v in c in c vpp (opt) ca 16 1 2 3 4 56 7 8 15 14 13 12 11 10 9 scl sda vpp l1 l2 17 shdn
lt3582/lt3582-5/lt3582-12 22 3582512fb lt3582 v in swp capp v neg C12v 85ma capp v pp sda scl ca gnd swn swn v outn v outp shdn input 4.5v to 5.5v v pos 12v 80ma l1 6.8h d1 c2 4.7f c6 10nf c5 10nf rampn rampp c3 c1 4.7f c4 1f d2 l2 6.8h reg0/otp0 = b0h reg1/otp1 = d8h reg2/otp2 = 03h d1-d2: diodes inc. b0540ws-7 l1-l2: coilcraft xpl2010-682 c1: 4.7f, 6.3v, x5r, 0805 c2: 4.7f, 16v, x5r, 0805 c3: 1 s 4.7f or 2 s 4.7f or 10f 16v, x5r, 0805 c4: 1f, 16v, x5r, 0603 c5-c6: 10nf, 0603 3582512 ta05a i 2 c interface optional on lt3582-12 load current (ma) 02040 80 60 15 10 5 0 20 25 output ripple (mv) 3582512 ta05b load current (ma) 20 04080 60 40 20 0 60 80 output ripple (mv) 3582512 ta05c 4.7f 16v 0805 x5r 10f 16v 0805 x5r 2 4.7f 16v 0805 x5r figure 13. 12v outputs from a single 5v input v outp ripple v outn ripple and c2 selection also see typical characteristics and front page for additional data applications information
lt3582/lt3582-5/lt3582-12 23 3582512fb typical application lt3582 v in swp capp v neg C5v 100ma (v in 2.7v) 125ma (v in 3.3v) capp v pp sda scl ca gnd swn swn v outn v outp shdn input 2.7v to 3.8v v pos 5v 100ma (v in 2.7v) 124ma (v in 3.3v) reg0/otp0 = 24h reg1/otp1 = 4ch reg2/otp2 = 03h d1-d2: diodes inc. b0540ws-7 l1-l2: coilcraft lps4018-682ml c1: 4.7f, 6.3v, x5r, 0805 c2-c3: 10f, 6.3v, x5r 0805 c4: 1f, 6.3v, x5r, 0603 c5-c6: 22nf, 0603 l1 6.8h d1 c2 10f c6 22nf c5 22nf rampn rampp c1 4.7f c3 10f d2 c4 1f l2 6.8h 3582512 ta02a i 2 c interface optional on lt3582-5 load current (ma) 0.1 efficiency (%) power loss (mw) 35 45 65 85 100 90 80 70 60 50 40 30 20 10 0 55 75 95 1 10 100 3582512 ta02b v in = 3.3v load current (ma) 0.1 efficiency (%) power loss (mw) 35 45 65 85 180 160 140 120 100 80 60 40 20 0 55 75 95 1 10 100 3582512 ta02c v in = 3.3v load current (ma) 0.1 efficiency (%) power loss (mw) 35 45 65 85 300 250 200 150 100 50 0 55 75 95 1 10 100 3582512 ta02d v in = 3.3v 5v outputs from a single 2.7v to 3.8v input ef? ciency and power loss, load from v outp to gnd ef? ciency and power loss, load from v outn to gnd ef? ciency and power loss, load from v outp to v outn
lt3582/lt3582-5/lt3582-12 24 3582512fb typical application lt3582 v in swp capp v neg C5v 100ma (v in 2.7v) 125ma (v in 3.3v) capp v pp sda scl ca gnd swn swn v outn v outp shdn input 2.7v to 3.8v v pos 5v 110ma (v in 2.7v) 150ma (v in 3.3v) reg0/otp0 = 24h reg1/otp1 = 4ch reg2/otp2 = 03h d1-d2: diodes inc. b0540ws-7 l1-l2: coilcraft lps4018-682ml c1: 4.7f, 6.3v, x5r, 0805 c2-c3: 10f, 6.3v, x5r, 0805 c4: 1f, 6.3v, x5r, 0603 c5-c6: 22nf, 0603 l1 6.8h d1 c2 10f rampn rampp c1 4.7f c6 22nf c5 22nf d2 c3 10f l2 6.8h 3582512 ta03 i 2 c interface optional on lt3582-5 5v outputs from a single 2.7v to 3.8v input (improved ef? ciency) ef? ciency and power loss, load from v outp to gnd load current (ma) 0.1 efficiency (%) power loss (mw) 35 45 65 85 80 70 60 50 40 30 20 10 0 55 75 95 1 10 100 3582512 ta03a v in = 3.3v
lt3582/lt3582-5/lt3582-12 25 3582512fb typical application lt3582 v in swp capp v neg C5v 100ma capp v pp sda scl ca gnd swn swn v outn i 2 c interface v outp shdn input 2.7v to 5.5v v pos 12v 38ma (v in = 2.7) 58ma (v in = 3.6) 95ma (v in = 5.5) reg0/otp0 = b0h reg1/otp1 = 4ch reg2/otp2 = 0bh d1-d2: diodes inc. b0540ws-7 l1-l2: coilcraft lps4018-682ml c1: 4.7f, 6.3v, x5r, 0805 c2: 10f, 6.3v, x5r, 0805 c3: 4.7f, 16v, x5r, 0805 c4: 1f, 16v, x5r, 0603 c5-c6: 22nf, 0603 l1 6.8h d1 c2 10f rampn rampp c1 4.7f c6 22nf c5 22nf d2 c4 1f c3 4.7f l2 6.8h 3582512 ta04a load current (ma) 0.1 efficiency (%) power loss (mw) 35 45 65 85 80 90 100 70 60 50 40 30 20 10 0 55 75 95 1 10 100 3582512 ta04b v in = 3.6v load current (ma) 0.1 efficiency (%) power loss (mw) 35 45 65 85 180 160 140 120 100 80 60 40 20 0 55 75 95 1 10 100 3582512 ta04c v in = 3.6v load current (ma) 0.1 efficiency (%) power loss (mw) 35 45 65 85 160 180 200 140 120 100 80 60 40 20 0 55 75 95 1 10 100 3582512 ta04d v in = 3.6v 12v and C5v outputs from a single 2.7v to 5.5v input ef? ciency and power loss, load from v outp to v outn ef? ciency and power loss, load from v outp to gnd ef? ciency and power loss, load from v outn to gnd
lt3582/lt3582-5/lt3582-12 26 3582512fb package description 3.00 p 0.10 (4 sides) recommended solder pad pitch and dimensions 1.45 p 0.05 (4 sides) note: 1. drawing conforms to jedec package outline mo-220 variation (weed-2) 2. drawing not to scale 3. all dimensions are in millimeters 4. dimensions of exposed pad on bottom of package do not include mold flash. mold flash, if present, shall not exceed 0.15mm on any side 5. exposed pad shall be solder plated 6. shaded area is only a reference for pin 1 location on the top and bottom of package pin 1 top mark (note 6) 0.40 p 0.10 bottom viewexposed pad 1.45 p 0.10 (4-sides) 0.75 p 0.05 r = 0.115 typ 0.25 p 0.05 1 pin 1 notch r = 0.20 typ or 0.25 s 45 o chamfer 15 16 2 0.50 bsc 0.200 ref 2.10 p 0.05 3.50 p 0.05 0.70 p 0.05 0.00 C 0.05 (ud16) qfn 0904 0.25 p 0.05 0.50 bsc package outline ud package 16-lead plastic qfn (3mm 3mm) (reference ltc dwg # 05-08-1691)
lt3582/lt3582-5/lt3582-12 27 3582512fb information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no representa- tion that the interconnection of its circuits as described herein will not infringe on existing patent rights. revision history rev date description page number b 11/09 revised title and add text to description revised pin con? guration added text to i 2 c interface section revised typical application drawings 1 2 11 22, 23, 24 (revision history begins at rev b)
lt3582/lt3582-5/lt3582-12 28 3582512fb linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 fax: (408) 434-0507 www.linear.com ? linear technology corporation 2009 lt 0110 rev b ? printed in usa related parts part description comments lt1944/lt1944-1(dual) dual output 350ma i sw , constant off-time, high ef? ciency step-up dc/dc converter v in : 1.2v to 15v, v out(max) = 34v, i q = 20a, i sd <1a, ms10 lt1945(dual) dual output, pos/neg, 350ma i sw , constant off-time, high ef? ciency step-up dc/dc converter v in : 1.2v to 15v, v out(max) = 34v, i q = 20a, i sd <1a, ms10 lt3463/lt3463a dual output, boost/inverter, 250ma i sw , constant off-time, high ef? ciency step-up dc/dc converter with integrated schottkys v in : 2.4v to 15v, v out(max) = 40v, i q = 40a, i sd <1a, dfn lt3471 dual output, boost/inverter, 1.3a i sw , 1.2mhz, high ef? ciency boost-inverting dc/dc converter v in : 2.4v to 16v, v out(max) = 40v, i q = 2.5ma, i sd <1a, dfn lt3472 dual output, boost/inverter, 0.35a i sw , 1.2mhz, high ef? ciency boost-inverting dc/dc converter v in : 2.2v to 16v, v out(max) = 34v, i q = 2.8ma, i sd <1a, dfn lt3477 42v, 3a, 3.5mhz boost, buck-boost, buck led driver v in : 2.5v to 25v, v out(max) = 40v, i q = analog/pwm, i sd <1a, qfn, tssop-20e lt3494/lt3494a 180/350ma (i sw ), low noise high ef? ciency step-up dc/dc converter v in : 2.3v to 16v, v out(max) = 40v, i q = 65a, i sd <1a, 2mm 3mm dfn lt3495/lt3495b/ lt3495-1/lt3495b-1 650/350ma (i sw ), low noise high ef? ciency step-up dc/dc converter v in : 2.5v to 16v, v out(max) = 40v, i q = 60a, i sd <1a, 2mm 3mm dfn lt1930/lt1930a 1a (i sw ), 1.2/2.2mhz, high ef? ciency step-up dc/dc converter v in : 2.6v to 16v, v out(max) = 34v, i q = 4.2/5.5ma, i sd <1a, thinsot? lt1931/lt1931a 1a (i sw ), 1.2/2.2mhz, high ef? ciency inverting dc/dc converter v in : 2.6v to 16v, v out(max) = 34v, i q = 4.2/5.5ma, i sd <1a, thinsot lt3467/lt3467a 1.1a (i sw ), 1.3/2.1mhz, high ef? ciency step-up dc/dc converter with soft-start v in : 2.4v to 16v, v out(max) = 40v, i q = 1.2ma, i sd <1a, thinsot lt1618 1.5a (i sw ), 1.4mhz, high ef? ciency step-up dc/dc converter v in : 1.6v to 18v, v out(max) = 35v, i q = 1.8ma, i sd <1a, ms10, dfn lt1946/lt1946a 1.5a (i sw ), 1.2/2.7mhz, high ef? ciency step-up dc/dc converter v in : 2.6v to 16v, v out(max) = 34v, i q = 3.2ma, i sd <1a, ms8e thinsot is a trademark of linear technology corporation. typical application lt3582 v in swp capp v neg C5v 90ma capp v pp sda scl ca gnd swn swn v outn i 2 c interface v outp shdn input 2.7v to 4.2v v pos 4.6v 100ma l1 1.5h d1 c2 10f c6 10nf c5 10nf rampn rampp c3 10f c1 10f d2 c4 10f l2 1.5h reg0/otp0 = 1ch reg1/otp1 = 4ch reg2/otp2 = 07h d1-d2: panasonic m21d3800l low v f schottky l1-l2: tdk mlp3216s1r5l c1-c4: taiyo yuden jmk212bj106mk, 6.3v, x5r 0805 c5-c6: 0402 x5r 3582512 ta06a load current (ma) 0.1 efficiency (%) power loss (mw) 30 40 60 80 350 300 250 200 150 100 50 0 50 70 90 1 10 100 3582512 ta06b v in = 3.3v tiny amoled power supply is 0.8mm (max) thin ef? ciency and power loss, load from v outp to v outn

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